Robert Horst's Resume

2000 – 5/01 Vice President, Research & Technology, 3ware Inc. Initiated and led project that resulted in industry’s first Ethernet System Area Network storage subsystem. Attended board meetings and contributed as member of senior management team. Filed 10 patent applications.

1999-2000 Director of Research, 3ware, Inc. Developed novel disk mirroring architecture and helped the company to grow from 15 to over 100 people. Participated in fund raising activities and prototype development.

1997-1999 Technical Director, Manager, Compaq Tandem Labs

- Manager of a small group developing hardware prototypes. Projects were directed at innovative uses of ServerNet in clustered systems.

1991-1997 Technical Director, Tandem Computers Inc.

- Consultant to upper management on architecture, strategy, university relations, patents, mergers and acquisitions.

- Primary architect of the ServerNet System Area Network. Internal and external champion of ServerNet. Wrote technical papers and made numerous presentations to technical audiences and customers.

- Founding member of Tandem Labs. Conceived and managed the first project to incorporate ServerNet on PCI cards for PC clustering. Started joint research projects with University of Illinois, Texas A&M University, and Boston University

- Technical liaison with Intel, Compaq and other partners.

1988-1991 Ph.D. student, University of Illinois.

Full time student and half-time Tandem consultant. Part of the three-person team starting the Tandem migration from proprietary CISC to MIPS RISC processors.

1983-1988 Senior Systems Architect, Tandem Computers Inc.

Principal architect of the NonStop Cyclone superscalar processor. Listed inventor on the industry's first superscalar patents.

Architectural consultant on the Integrity S2 system -- a fault-tolerant RISC-based Unix system.

Architectural consultant on the NonStop VLX processor -- Tandem's first gate-array based machine. Participated in technology evaluation and selection.

1980-1983 Project Leader, Tandem Computers Inc.

Architecture definition and design of the Tandem NonStop TXP system. The TXP was the high-end of Tandem's line of fault-tolerant, distributed memory multiprocessors and generated over $1B in system revenues. Participated in CAD tool development and test system development.

1976-1980 Development Engineer, Hewlett-Packard Co.

Designed ECL hardware for the micro-sequencer and cache of the HP3000 Series 64 processor. Designed a test system for the processor cards using pseudo-random scan and signature analysis;

Awards

B.S.E.E. Summa Cum Laude 1975

Tandem Outstanding Performer Award 1983, 1995

Tandem Technical Excellence Award 1987

Daniel A. Slotnick Award for Most Original Paper, ICPP, 1990

Tandem President's Award, 1992

Information Week selection of ServerNet as one of the “Most Important Products” in both 1996 and 1997.

Distinguished Alumni Award for “Pioneering Contributions to Fault-tolerant Computer Architecture,” University of Illinois department of Electrical and Computer Engineering, 1998.

IEEE Fellow. Elected “for contributions to the architecture and design of fault tolerant systems and networks,” 2001

Professional Service and Activities

Program Committee: Int. Symposium on Fault Tolerant Computing, 1991, 1997, 1999.

Reviewer: Int. Symposium on Computer Architecture, ACM Doctoral Dissertation Award, Int. Symposium on Fault Tolerant Computing, IEEE Computer, IEEE Transactions on Reliability, IEEE Transactions on Computers, National Science Foundation

Lectures: Stanford University, University of California at Santa Cruz, University of Illinois, University of Texas, University of Minnesota, University of California at Berkeley.

Expert witness: Testified as an expert in Fault-tolerant Computing for the State of California, 1992.

Videotape

"ServerNet and the Emergence of System Area Networks," University Video Communications, Oct. 1995. See http://www.uvc.com

Selected Publications

Fault Tolerance

[1] R. Horst, "Reliable Design of High-speed Cache and Control Store Memories," Proc. 19th Int. Symp. Fault-Tolerant Computing, June 1989.

[2] J. Bartlett, W. Bartlett, R. Carr, D. Garcia, J. Gray, R. Horst, R. Jardine, et al., "Fault Tolerance in Tandem Computer Systems," in Reliable Computer Systems, D. P. Siewiorek and R. S. Swarz, Eds., Bedford, MA: Digital Press, 1992.

[3] R. Horst, D. Jewett, D. Lenoski, "The Risk of Data Corruption in Microprocessor-based Systems," Proc. 23rd International Symposium on Fault-tolerant Computing, June 1993.

[4] R. Horst, "Massively Parallel Systems You Can Trust," COMPCON Digest of Papers, San Francisco, CA, Feb. 28-March 4, 1994.

[5] W. E. Baker, et al., "A Flexible ServerNet-based Fault-Tolerant Architecture," in Proc. 25th Int. Symp. Fault-Tolerant Computing, Pasadena, CA, June 27-30 1995.

CPU Architecture

[1] R. Horst, "A Linear-Array WSI Architecture for Improved Yield and Performance," in Proc. Int. Conf. WSI, San Francisco, CA, pp. 85-91, Jan. 1990.

[21] R. Horst, "Task Flow Computer Architecture," in Proc. Int. Conf. Parallel Processing, Vol. I, pp. 533-540, Aug. 1990.

[3] R. Horst, "Task Flow: A Novel Approach to Fine-grain Wafer-scale Parallel Computing," Coordinated Science Lab. Report CRHC-91-15, University of Illinois, April 1991.

[4] R. Horst, R. Harris, and R. Jardine, "Multiple Instruction Issue in the NonStop Cyclone Processor," in Proc. 17th Int. Symp. Computer Architecture, May 1990.

[5] R. W. Horst, "Task-Flow Architecture for WSI Parallel Processing," Computer, vol. 25, no. 4, pp. 10-18, April 1992.

Storage

[1] J. Gray, B. Horst, and M. Walker, "Parity striping of disk arrays: Low cost reliable storage with acceptable throughput," in Proc. 16th Int. Conf. on Very Large Databases, Brisbane, Australia, pp. 148-161, Aug. 1990.

[2] R. Horst, J. McDonald, B. Alessi, “Beyond RAID: An Architecture for Improving PC Fault Tolerance and Performance, Digest of Fast Abstracts, 29th Int. Symp. Fault-Tolerant Computing, June 1999.

[3] R. Horst, “TwinStor Technology: A Compelling Case for Multiple Drives in PCs, Servers and Workstations,” 3ware Technical Report TR-1999-2, 3ware, Inc., August 1999.

[4] L. Chung, J. Gray, B. Worthington, R. Horst, “Study of Random and Sequential IO on Windows 2000™”, http://research.microsoft.com/BARC/Sequential_IO/.

[5] R. Horst, “Storage Networking: The Killer Application for Gigabit Ethernet,” dmDirect Business Intelligence Newsletter, http://www.dmreview.com. April 20, 2001.

Networks

[1] R. Horst, "TNet: A Reliable System Area Network," IEEE Micro, vol. 15, no. 1, pp. 37-45, February 1994.

[2] R. Horst, "ServerNet Deadlock Avoidance and Fractahedral Topologies," in Proc. 10th Int'l Parallel Processing Symposium, Honolulu, Hawaii, pp. 274-280, 1995.

[3] R. Horst and D. Garcia, "ServerNet SAN I/O Architecture," Proc. Hot Interconnects V, August 1997.

[4] R. Horst, "A Fault Model for System Area Networks," FTCS-28 Fast Abstract, June 1998.

[5] D.R Avresky, V. Shurbanov, R. Horst, “The effect of router arbitration policy on scalability of ServerNet Topologies,” Microprocessors and Microsystems 21, pp 545-561, 1998.

[6] D.R Avresky, V. Shurbanov, R. Horst, W. Watson, L. Young, D. Jewett. “Performance Modeling of ServerNet SAN Topologies,” Journal of Supercomputing, V. 14, pp. 19-37, 1999.

[7] D.R Avresky, V. Shurbanov, R. Horst, “Optimizing router arbitration in point-to-point networks,” Computer Communications, 22, pp 608-620, 1999.

[8] D.R Avresky, V. Shurbanov, R. Wilkinson, R. Horst, W. Watson, L. Young, “ Maximum delivery time and hot spots in ServerNet topologies, Computer Networks 31, pp. 1891-1910, 1999.

[9] A. Hossain, S. Kang, R. Horst, “ ServerNet and ATM Interconnects: Comparison for Compressed Video Transmission,” Journal of Communications and Networks, V. 1 No. 2, June 1999.

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